In a semiconductor integrated circuit, there is a case in which an integrated circuit does not normally operate if delay time of a circuit within the integrated circuit does not satisfy a specified condition. On the other hand, in manufacturing the integrated circuit, a circuit characteristic accompanies a variation due to a manufacturing condition etc. As a result, a variation occurs in the delay time of a circuit within the integrated circuit to be manufactured. Such being the case, for designing the integrated circuit, a designer verifies based on timing analysis whether the circuit in the integrated circuit normally operates or not by setting an allowable value of the delay time after taking account of a margin to some extent in the delay time of the circuit within the integrated circuit.
A conventional technique known in the timing analysis for designing the integrated circuit is a technique of statistically processing the variation of the delay time of the circuit within the integrated circuit. SSTA (Statistical Static Timing Analysis) is proposed as an analyzing method of statistically processing the delay time of the circuit.
The SSTA involves receiving a feedback from a measurement result of the delay time of each of a variety of integrated circuits manufactured on, e.g., various manufacturing lines and obtaining a delay time distribution of the circuit. Therefore, when putting a focus on one single integrated circuit, there is a case where the variation of the delay time of the integrated circuit is not coincident with the variation of the delay time on the manufacturing line for the variety of integrated circuits. Consequently, the circuit within the focused integrated circuit contains a possibility of setting an excessive margin (or deficiency of margin) in the delay time.    [Patent document 1] Japanese Laid-open Patent Publication No. 2005-19524    [Patent document 2] Japanese Laid-open Patent Publication No. 2008-134826    [Patent document 3] Japanese Laid-open Patent Publication No. 2002-110489